1. Field of the Invention
This invention relates to the automatic compensation of phase variations in the delay element of a differentially coherent signal detector used for demodulation of phase shift keyed signals.
2. Description of the Prior Art
Binary phase shift keying (PSK) modulation is widely used in data communications. This modulation technique references the phase associated with a particular bit to the phase associated with a prior bit. As an example, if the phase of the Nth bit is X then the phase of the next bit will be X+90.degree. if this next bit is a 1 and X-90.degree. if this next bit is a 0, or vice versa. Or, if X is the phase of the Nth bit then the phase of the next bit will be X if this next bit is a 1, and X+180.degree. if this next bit is a 0, or vice versa.
There are two basic approaches towards demodulating these signals. One method involves coherent signal detection using a local reference carrier as shown in FIG. 1. The received signal at 10, sin (WT+PH), is mixed by mixer 11 with a signal cos (WT) from a local reference oscillator 12, where W is the frequency, T is the time and PH is the phase angle. The output of mixer 11 at 13 is 1/2 sin (PH)+1/2 sin (2WT+PH). The phase of the received signal can be extracted from the baseband portion of this signal, 1/2 sin (PH). This technique involves comparing the phase of the received signal with the phase of a local reference carrier.
The main difficulties with this approach involve synchronizing the phase and matching the frequency of the local carrier with that of the original transmitter carrier.
A second approach for demodulating these signals involves a differentially coherent signal detection scheme as shown in FIG. 2. The received signal at 20, sin (WT+PI), where PI represents the phase angle, is split by hybrid splitter 21. The inphase portion is applied to delay element 22. The output of the delay element, the delayed signal sin (WT+PJ), where PJ represents the phase of the delayed signal, is connected to the input of mixer 23. The quadrature portion of the signal from hybrid splitter 21, cos (WT+PI), is fed to mixer 23. The output of mixer 23 is 1/2 sin (2WT+PI+PJ)-1/2 sin (PI-PJ). The relative phase shift between the received bit and the prior bit can be extracted from the baseband portion of the signal, 1/2 sin (PI-PJ), emerging at 24 from mixer 23. This technique involves comparing the phase of the received bit with the phase of a prior bit. No local reference oscillator is needed; however, the phase of the prior bit must be saved for comparison. This can be accomplished by a delay element.
For optimal detection, the signals associated with the current and prior bit must simultaneously arrive at mixer 23. To accomplish this, the time delay introduced by the delay element 22 must be stable. Unfortunately, this stability is affected by temperature, age, and fluctuations in the frequency of the signal. The purpose of this invention is to insure maximum signal at the phase detector by automatically compensating for phase shifts introduced by the delay element.
A prior art search was conducted and the following patents were uncovered: U.S. Pat. Nos. 4,055,814; 3,919,653; 3,911,219; 3,906,376; 4,100,499; 3,787,775; 3,993,956; and 3,550,021 all require a voltage controlled oscillator. My invention uses differential coherent detection and does not require such a local reference oscillator.
U.S. Pat. Nos. 3,990,015; 3,991,377; 3,944,939; 3,838,350; and 3,794,921 all use delays for demodulation, but none of these systems provide a means to compensate for phase shift variations in the delay as does my invention.
U.S. Pat. Nos. 4,088,957; 3,818,346; and 3,843,931 do not use delays for demodulation nor do they have a phase shift correction mechanism as does my invention.
U.S. Pat. Nos. 3,305,798 and 4,053,932 do not involve coherent signal detection and are thus not applicable.
U.S. Pat. No. 4,091,331 utilizes a phase error predictor which requires the recovery of the clock signal. My invention operates directly with the signals and requires neither clock recovery nor bit synchronization.
U.S. Pat. No. 4,041,533 compensates for a variable delay in an analog video baseband signal; it can not be used to detect phase shift keyed signals or delay such signals. Unlike the present invention, the circuit requires introduction of reference pulses.